{"added":null,"apiVersion":1,"behindSince":"2026-09-11","buildDepends":[],"categories":["cad"],"comment":"Yosys Open SYnthesis Suite","compare":"/compare/yosys/index.json","dependentCount":null,"description":"Yosys is a framework for Verilog RTL synthesis.  It currently has\nextensive Verilog-2005 support and provides a basic set of synthesis\nalgorithms for various application domains.","flavors":[],"html":"https://daemonports.org/dragonfly/cad/yosys/","kind":"port","lastUpdate":null,"license":["ISCL"],"maintainer":"yuri@FreeBSD.org","name":"yosys","newest":false,"newestVersion":"0.70","noVulnData":false,"origin":"cad/yosys","otherSystems":[{"behindSince":"2026-10-20","maintainer":"yuri@FreeBSD.org","origin":"cad/yosys","path":"/cad/yosys/","system":"FreeBSD","updated":"2026-09-29","version":"0.69_1"},{"maintainer":"Thomas Dettbarn \u003cdettus@dettus.net\u003e","newest":true,"noVulnData":true,"origin":"cad/yosys","path":"/openbsd/cad/yosys/","system":"OpenBSD","updated":"2026-10-22","version":"0.70p1"},{"behindSince":"2026-09-11","maintainer":"ports@MidnightBSD.org","noVulnData":true,"origin":"cad/yosys","path":"/midnightbsd/cad/yosys/","system":"MidnightBSD","version":"0.52_1"},{"behindSince":"2026-10-20","maintainer":"yuri@FreeBSD.org","noVulnData":true,"origin":"cad/yosys","path":"","system":"GhostBSD","version":"0.69"}],"packages":null,"pkgName":"yosys-0.36","related":null,"repository":"DPorts","requiredBy":["cad/py-edalize"],"requiredByCount":1,"runDepends":["devel/google-perftools","devel/libffi","devel/readline","lang/python311","lang/tcl86","math/yices","shells/bash","x11/py-xdot"],"status":null,"system":"dragonfly","systemLabel":"DragonFly","version":"0.36","versions":null,"vulnerabilities":null,"www":"https://yosyshq.net/yosys/"}