{"added":null,"apiVersion":1,"behindSince":null,"buildDepends":[],"categories":["cad"],"comment":"Project organizer for VHDL and Verilog RTL hardware designs","compare":null,"dependentCount":null,"description":"ChipVault is a VHDL and Verilog Chip Design Organization tool which improves\ndesign efficiency by:\n   - Providing the ability to Navigate and Edit files Hierarchically.\n   - Automatically generating Schematic Component Port views of VHDL and\n     Verilog RTL files.\n   - Automating RTL instantiation and template generation.\n   - Providing Revision Control (designed for HW, not SW development).\n   - Supporting External Tool Hooks (bottom-up vcoms,etc).\n   - Providing an Issue Tracking Log with sorting.\n   - Providing Netlist sorting and hierarchy viewing.\n   - Supporting web-sharing of RTL files (both encrypted and clear).\n   - Fast and Nimble.","flavors":[],"html":"https://daemonports.org/midnightbsd/cad/chipvault/","kind":"port","lastUpdate":null,"license":[],"maintainer":"ports@MidnightBSD.org","name":"chipvault","newest":true,"newestVersion":"200607","noVulnData":true,"origin":"cad/chipvault","otherSystems":[{"maintainer":"ports@FreeBSD.org","newest":true,"origin":"cad/chipvault","path":"/cad/chipvault/","system":"FreeBSD","version":"200607"},{"maintainer":"ports@FreeBSD.org","newest":true,"origin":"cad/chipvault","path":"/dragonfly/cad/chipvault/","system":"DragonFly","version":"200607"},{"maintainer":"ports@FreeBSD.org","newest":true,"noVulnData":true,"origin":"cad/chipvault","path":"","system":"HardenedBSD","version":"200607"},{"maintainer":"ports@FreeBSD.org","newest":true,"noVulnData":true,"origin":"cad/chipvault","path":"","system":"GhostBSD","version":"200607"}],"packages":null,"pkgName":"chipvault-200607","related":null,"repository":"mports","requiredBy":[],"requiredByCount":0,"runDepends":[],"status":null,"system":"midnightbsd","systemLabel":"MidnightBSD","version":"200607","versions":null,"vulnerabilities":null,"www":"https://chipvault.sourceforge.net/"}