BSD Ports

cad/py-verilog-parser 0.0.7 FreeBSD

Lark-based parser for structural Verilog netlists

System
FreeBSD
Repository
FreeBSD ports
Maintainer
[email protected]
License
AGPLv3+
Categories
cad, python
Package size
17.6 KiB, 81.0 KiB installed

Description

Lark-based parser for Verilog netlists (structural Verilog without behavioral statements). This is meant to be used to read netlists as generated by HDL logic synthesizers such as Yosys.

Install

Binary package:

pkg install py312-verilog_parser

From the ports tree:

cd /usr/ports/cad/py-verilog-parser/ && make install clean

To depend on this port in another port's Makefile:

RUN_DEPENDS=	py312-verilog_parser>0:cad/py-verilog-parser

Packages

The version each package repository carries. “-” means the repository builds no package of it, “n/a” that there is no such repository.

Repositoryaarch64amd64armv6armv7i386
FreeBSD:14:latest0.0.70.0.7--0.0.7
FreeBSD:14:quarterly0.0.70.0.7n/a-0.0.7
FreeBSD:15:latest0.0.70.0.7n/a--
FreeBSD:15:quarterly0.0.70.0.7n/an/an/a
FreeBSD:16:latest0.0.70.0.7n/an/an/a
FreeBSD:16:quarterlyn/an/an/an/an/a

Dependencies

As this port's Makefile names them.

Build 2

The full lists below include those, and their dependencies in turn.

Build dependencies 19
Run dependencies 7

No port depends on this one.

Configuration

No options to configure.

USES
python
Service scripts
none

Files

distinfo 1
FileSizeSHA256
verilog_parser-0.0.7.tar.gz7197dbe6db18bc74398fa481ca373205818065cac2ac0e165886ce373b01bdf8e0f7
Master sites 1
  • PYPI

Commit history 0

No commits in the history this site was built from.