BSD Ports

emulators/riscv-isa-sim 1.1.0.20240531 FreeBSD

Spike, a RISC-V ISA Simulator

System
FreeBSD
Repository
FreeBSD ports
Maintainer
[email protected]
License
BSD3CLAUSE
Categories
emulators
Package size
5677.4 KiB, 56383.2 KiB installed

Description

Spike, a RISC-V ISA Simulator

The RISC-V ISA Simulator implements a functional model of one or more RISC-V processors.

In the other systems

SystemPortVersion
FreeBSDemulators/riscv-isa-sim1.1.0.20240531
DragonFlyemulators/riscv-isa-sim1.1.0.20240531
HardenedBSDemulators/riscv-isa-sim1.1.0.20240531
GhostBSDemulators/riscv-isa-sim1.1.0.20240531

Install

Binary package:

pkg install riscv-isa-sim

From the ports tree:

cd /usr/ports/emulators/riscv-isa-sim/ && make install clean

To depend on this port in another port's Makefile:

RUN_DEPENDS=	riscv-isa-sim>0:emulators/riscv-isa-sim
LIB_DEPENDS=	libcustomext.so:emulators/riscv-isa-sim

Packages

The version each package repository carries. “-” means the repository builds no package of it, “n/a” that there is no such repository.

Repositoryaarch64amd64armv6armv7i386
FreeBSD:14:latest1.1.0.202405311.1.0.20240531g_202110151.1.0.20240531-
FreeBSD:14:quarterly1.1.0.202405311.1.0.20240531n/a1.1.0.20240531-
FreeBSD:15:latest1.1.0.202405311.1.0.20240531n/a1.1.0.20240531-
FreeBSD:15:quarterly1.1.0.202405311.1.0.20240531n/an/an/a
FreeBSD:16:latest1.1.0.202405311.1.0.20240531n/an/an/a
FreeBSD:16:quarterlyn/an/an/an/an/a

Dependencies

The Makefile names none itself; they come from USES and USE_*.

The full lists below include those, and their dependencies in turn.

Build dependencies 3

No port depends on this one.

Configuration

No options to configure.

USES
compiler:c++11-lang gmake shebangfix
Service scripts
none

Files

pkg-plist 68
  • bin/elf2hex
  • bin/spike
  • bin/spike-dasm
  • bin/spike-log-parser
  • bin/termios-xspike
  • bin/xspike
  • include/fdt/fdt.h
  • include/fdt/libfdt.h
  • include/fdt/libfdt_env.h
  • include/fesvr/byteorder.h
  • include/fesvr/config.h
  • include/fesvr/context.h
  • include/fesvr/device.h
  • include/fesvr/dtm.h
  • include/fesvr/elf.h
  • include/fesvr/elfloader.h
  • include/fesvr/htif.h
  • include/fesvr/htif_hexwriter.h
  • include/fesvr/htif_pthread.h
  • include/fesvr/memif.h
  • include/fesvr/option_parser.h
  • include/fesvr/rfb.h
  • include/fesvr/syscall.h
  • include/fesvr/term.h
  • include/fesvr/tsi.h
  • include/riscv/abstract_device.h
  • include/riscv/abstract_interrupt_controller.h
  • include/riscv/cachesim.h
  • include/riscv/cfg.h
  • include/riscv/common.h
  • include/riscv/csrs.h
  • include/riscv/debug_defines.h
  • include/riscv/debug_module.h
  • include/riscv/debug_rom_defines.h
  • include/riscv/decode.h
  • include/riscv/devices.h
  • include/riscv/disasm.h
  • include/riscv/dts.h
  • include/riscv/encoding.h
  • include/riscv/entropy_source.h
  • include/riscv/extension.h
  • include/riscv/isa_parser.h
  • include/riscv/log_file.h
  • include/riscv/memtracer.h
  • include/riscv/mmu.h
  • include/riscv/platform.h
  • include/riscv/processor.h
  • include/riscv/rocc.h
  • include/riscv/sim.h
  • include/riscv/simif.h
  • include/riscv/trap.h
  • include/riscv/triggers.h
  • include/riscv/vector_unit.h
  • include/softfloat/internals.h
  • include/softfloat/platform.h
  • include/softfloat/primitiveTypes.h
  • include/softfloat/primitives.h
  • include/softfloat/softfloat.h
  • include/softfloat/softfloat_types.h
  • include/softfloat/specialize.h
  • lib/libcustomext.so
  • lib/libdisasm.a
  • lib/libfesvr.a
  • lib/libriscv.so
  • lib/libsoftfloat.so
  • libdata/pkgconfig/riscv-disasm.pc
  • libdata/pkgconfig/riscv-fesvr.pc
  • libdata/pkgconfig/riscv-riscv.pc
distinfo 1
FileSizeSHA256
riscv-riscv-isa-sim-1.1.0-20240531-00dfa28_GH0.tar.gz4928485489098fd67d2d8cfbc714a6e93464ca702125ab0308a523de8528f474a5c80d

Commit history 0

No commits in the history this site was built from.