cad/silice g20221229_2 MidnightBSD

Language that simplifies prototyping and writing algorithms for FPGAs

System: MidnightBSD
Repository: mports
Maintainer: [email protected]
License: gpl3
Categories: cad

Description

Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.

In the other systems

The newest version among them is g20260322, as upstream numbers it.

System

Port

Version

Vulnerabilities

Status

Maintainer

Last update

MidnightBSD

cad/silice

g20221229_2

no data

[email protected]

FreeBSD

cad/silice

g20260322_1 newest

none known

[email protected]

GhostBSD

cad/silice

g20260322_1 newest

no data

[email protected]

Install

Binary package:

mport install silice

From mports:

cd /usr/mports/cad/silice && make install clean

To depend on this port in another port's Makefile:

RUN_DEPENDS=	silice>0:cad/silice

Dependencies

As this port's Makefile names them.

Build 1

bash : shells/bash

Runtime 1

${PYTHON_PKGNAMEPREFIX}edalize>0 : cad/py-edalize

Build dependencies 1

shells/bash

Run dependencies 1

cad/py-edalize

No port depends on this one.

Configuration

No options to configure.

USES: cmake:noninja java python shebangfix
Service scripts: none

Files

pkg-plist 108

bin/silice
bin/silice-make.py
share/silice/frameworks/boards/README.md
share/silice/frameworks/boards/bare/bare.sh
share/silice/frameworks/boards/bare/bare.v
share/silice/frameworks/boards/bare/board.json
share/silice/frameworks/boards/boards.json
share/silice/frameworks/boards/crosslink_nx_evn/board.json
share/silice/frameworks/boards/crosslink_nx_evn/crosslink_nx_evn.pdc
share/silice/frameworks/boards/crosslink_nx_evn/crosslink_nx_evn.sh
share/silice/frameworks/boards/crosslink_nx_evn/crosslink_nx_evn.v
share/silice/frameworks/boards/de10nano/board.json
share/silice/frameworks/boards/de10nano/build.sdc
share/silice/frameworks/boards/de10nano/de10nano.v
share/silice/frameworks/boards/de10nano/pins.tcl
share/silice/frameworks/boards/ecpix5/board.json
share/silice/frameworks/boards/ecpix5/ecpix5.lpf
share/silice/frameworks/boards/ecpix5/ecpix5.v
share/silice/frameworks/boards/fomu/board.json
share/silice/frameworks/boards/fomu/fomu-hacker.pcf
share/silice/frameworks/boards/fomu/fomu-hacker.sh
share/silice/frameworks/boards/fomu/fomu-pvt1.pcf
share/silice/frameworks/boards/fomu/fomu-pvt1.sh
share/silice/frameworks/boards/fomu/fomu.v
share/silice/frameworks/boards/formal/board.json
share/silice/frameworks/boards/formal/formal.sh
share/silice/frameworks/boards/formal/formal.v
share/silice/frameworks/boards/icarus/board.json
share/silice/frameworks/boards/icarus/icarus.sh
share/silice/frameworks/boards/icarus/icarus.v
share/silice/frameworks/boards/icebitsy/board.json
share/silice/frameworks/boards/icebitsy/icebitsy.pcf
share/silice/frameworks/boards/icebitsy/icebitsy.v
share/silice/frameworks/boards/icebreaker/board.json
share/silice/frameworks/boards/icebreaker/icebreaker.pcf
share/silice/frameworks/boards/icebreaker/icebreaker.sh
share/silice/frameworks/boards/icebreaker/icebreaker.v
share/silice/frameworks/boards/icestick/board.json
share/silice/frameworks/boards/icestick/icestick.pcf
share/silice/frameworks/boards/icestick/icestick.sh
share/silice/frameworks/boards/icestick/icestick.v
share/silice/frameworks/boards/littlebee/board.json
share/silice/frameworks/boards/littlebee/littlebee.cst
share/silice/frameworks/boards/littlebee/littlebee.sh
share/silice/frameworks/boards/littlebee/littlebee.v
share/silice/frameworks/boards/mch2022/board.json
share/silice/frameworks/boards/mch2022/mch2022.pcf
share/silice/frameworks/boards/mch2022/mch2022.sh
share/silice/frameworks/boards/mch2022/mch2022.v
share/silice/frameworks/boards/minimal/board.json
share/silice/frameworks/boards/minimal/minimal.sh
share/silice/frameworks/boards/minimal/minimal.v
share/silice/frameworks/boards/mojov3/board.json
share/silice/frameworks/boards/mojov3/mojov3.ucf
share/silice/frameworks/boards/mojov3/mojov3.v
share/silice/frameworks/boards/orangecrab/board.json
share/silice/frameworks/boards/orangecrab/orangecrab.sh
share/silice/frameworks/boards/orangecrab/orangecrab.v
share/silice/frameworks/boards/orangecrab/pinout.lpf
share/silice/frameworks/boards/riegel/board.json
share/silice/frameworks/boards/riegel/riegel.pcf
share/silice/frameworks/boards/riegel/riegel.v
share/silice/frameworks/boards/techgraph/board.json
share/silice/frameworks/boards/techgraph/techgraph.sh
share/silice/frameworks/boards/techgraph/techgraph.v
share/silice/frameworks/boards/ulx3s/board.json
share/silice/frameworks/boards/ulx3s/ulx3s.lpf
share/silice/frameworks/boards/ulx3s/ulx3s.sh
share/silice/frameworks/boards/ulx3s/ulx3s.v
share/silice/frameworks/boards/verilator/board.json
share/silice/frameworks/boards/verilator/verilator.sh
share/silice/frameworks/boards/verilator/verilator.v
share/silice/frameworks/libraries/memory_ports.si
share/silice/frameworks/libraries/riscv/ice-v-dual/config_c.ld
share/silice/frameworks/libraries/riscv/ice-v-dual/crt0.s
share/silice/frameworks/libraries/riscv/ice-v-dual/header.h
share/silice/frameworks/libraries/riscv/ice-v-dual/riscv-soc.si
share/silice/frameworks/libraries/riscv/ice-v/config_c.ld
share/silice/frameworks/libraries/riscv/ice-v/crt0.s
share/silice/frameworks/libraries/riscv/ice-v/header.h
share/silice/frameworks/libraries/riscv/ice-v/riscv-soc.si
share/silice/frameworks/libraries/riscv/riscv-compile.lua
share/silice/frameworks/templates/bram_generic.v.in
share/silice/frameworks/templates/bram_wmask_byte.v.in
share/silice/frameworks/templates/brom_generic.v.in
share/silice/frameworks/templates/dualport_bram_altera.v.in
share/silice/frameworks/templates/dualport_bram_generic.v.in
share/silice/frameworks/templates/dualport_bram_wmask_byte.v.in
share/silice/frameworks/templates/simple_dualport_bram_generic.v.in
share/silice/frameworks/templates/simple_dualport_bram_wmask_byte.v.in
share/silice/frameworks/templates/simple_dualport_bram_wmask_half_bytes.v.in
share/silice/frameworks/verilator/README.md
share/silice/frameworks/verilator/SPIScreen.cpp
share/silice/frameworks/verilator/SPIScreen.h
share/silice/frameworks/verilator/VgaChip.cpp
share/silice/frameworks/verilator/VgaChip.h
share/silice/frameworks/verilator/display.cpp
share/silice/frameworks/verilator/display.h
share/silice/frameworks/verilator/flyover_simul.gif
share/silice/frameworks/verilator/sdr_sdram.cpp

The first 100 are listed.

distinfo 4

File

Size

SHA256

sylefeb-Silice-g20221229-6a2beda_GH0.tar.gz

4.2949179e+07

5577d91ccac7e26204a034d262faa6107bbf06fdefe7107b3a5670364384f59c

sylefeb-LibSL-small-b1942d5_GH0.tar.gz

72760

dbea9ba30c4e40e3e9e6da840e90eb9e0a91b0355dc3ae0e72602d70d718d8fd

sylefeb-tinygpus-e6429ac_GH0.tar.gz

1.435993e+06

5e1cdfae1b81402acbeb118f350537599fd74cb8e2bc486ea6cb753ffe8f0d05

ultraembedded-fat_io_lib-0ef5c2b_GH0.tar.gz

52464

a88b5a3b0707931e7b2689d8f886b7dac53c9c4262aa9b3938d91a065c114079