BSD Ports

cad/py-PyRTL 1.0.3 NetBSD

Register-transfer-level hardware design and simulation

System
NetBSD
Repository
pkgsrc
Maintainer
[email protected]
Last update
Commit
30ae6626e6
License
modified-bsd
Categories
cad, python
Package size
369.3 KiB, 2947.8 KiB installed

Description

PyRTL provides a collection of classes for pythonic register-transfer level design, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility rather than performance or optimization is the overarching goal.

Install

Binary package:

pkgin install py311-PyRTL

From pkgsrc:

cd /usr/pkgsrc/cad/py-PyRTL && make install clean

Packages

The version each package repository carries. “-” means the repository builds no package of it, “n/a” that there is no such repository.

RepositoryVersion
NetBSD 10.1 x86_641.0.3
NetBSD 10.1 aarch640.12nb1
SmartOS / illumos x86_641.0.3
macOS 15 arm641.0.3

Dependencies

Run dependencies 1

No port depends on this one.

Configuration

No options to configure.

Service scripts
none
Flavors
py312-PyRTL-1.0.3, py313-PyRTL-1.0.3, py314-PyRTL-1.0.3

Commit history 2

DateCommitCreditsLog message
30ae6626e6 ryoon cad/py-PyRTL: Update to 1.0.3
Changelog: [1.0.3] - 2026-08-04 Added * name_scope is a context manager that prepends string prefixes to WireVector and MemBlock names. Changed * sign_extended and zero_extended no longer generate slice (s) LogicNets. * When concat is called with Const args, the constants are immediately concatenated, returning a new Const. * Improved render_trace's ASCII output. Fixed * Fixed an output_to_verilog bug where arithmetic expressions may truncate due to inlining. * Fixed several minor Windows compatibility issues around Unicode and testing. Enabled continuous Windows testing via GitHub Actions.
f56cf35584 ryoon cad/py-PyRTL: Update to 1.0.2
Changelog: ## [1.0.2] - 2026-07-22 ### Fixed - Fixed a `CompiledSimulation` `arm64` bug introduced in `1.0.1`. Added an `arm64` GitHub workflow to catch such regressions in the future. ## [1.0.1] - 2026-07-22 ### Changed - Significant `Simulation` performance speedups (tested with [`pyrtlnet`](https://github.com/UCSBarchlab/pyrtlnet)): class | method | speedup ---: | :--- | ---: `Simulation` | `step()` | 40% `FastSimulation` | `__init__()` | 10% `FastSimulation` | `step()` | 15% `CompiledSimulation` | `__init__()` | 65% `CompiledSimulation` | `step()` | 30% - Documentation improvements. ### Fixed - Fixed a `CompiledSimulation` bug when the first arg to `concat` crosses a 64-bit boundary in the `concat`'s output.