cad/opensta 2.2.0p2 OpenBSD

OpenSTA is a gate level static timing verifier. As a stand-alone executable it can be used to verify the timing of a design using standard file formats:

• Verilog netlist
• Liberty library
• SDC timing constraints
• SDF delay annotation
• SPEF parasitics

OpenSTA uses a TCL command interpreter to read the design, specify timing constraints and print timing reports.