BSD Portscad/yosys 0.52_1 MidnightBSD
Yosys Open SYnthesis Suite
- System
- MidnightBSD
- Repository
- mports
- Maintainer
- [email protected]
- License
- iscl
- Categories
- cad
Description
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
In the other systems
The newest version among them is 0.70, as upstream numbers it.
| System | Port | Version | Vulnerabilities | Status | Maintainer | Last update |
|---|---|---|---|---|---|---|
| MidnightBSD | cad/yosys | 0.52_1 behind since 2026-09-11 | no data | - | [email protected] | - |
| FreeBSD | cad/yosys | 0.69_1 behind since 2026-10-20 | none known | - | [email protected] | 2026-09-29 |
| OpenBSD | cad/yosys | 0.70p1 newest | no data | - | Thomas Dettbarn <[email protected]> | 2026-10-22 |
| DragonFly | cad/yosys | 0.36 behind since 2026-09-11 | none known | - | [email protected] | - |
| GhostBSD | cad/yosys | 0.69 behind since 2026-10-20 | no data | - | [email protected] | - |
Install
Binary package:
mport install yosysFrom mports:
cd /usr/mports/cad/yosys && make install cleanTo depend on this port in another port's Makefile:
RUN_DEPENDS= yosys>0:cad/yosysDependency graph
Ports that need it on the left, what it needs to run on the right; at most 8 of each. "Dependencies" below lists them all.
Dependencies
As this port's Makefile names them.
Build 4
abc: cad/abcbash: shells/bashcxxopts>0: devel/cxxoptsgawk: lang/gawk
Library 1
libffi.so: devel/libffi
Runtime 2
bash: shells/bashxdot: x11/py-xdot
Test 1
iverilog: cad/iverilog
Build dependencies 5
Run dependencies 3
Required by 3
Configuration
Options name: cad_yosys
| Option | Default | Description |
|---|---|---|
| CVC5 | off | CVC SAT Solver |
| TCMALLOC | on | |
| YICES | on | Yices SAT Solver |
| Z3 | off | Z3 SAT Solver |
- USES
- bison compiler:c++11-lang gmake pkgconfig python readline shebangfix tcl
- Service scripts
- none
Files
pkg-plist 324
- bin/yosys
- bin/yosys-config
- bin/yosys-filterlib
- bin/yosys-smtbmc
- bin/yosys-witness
- share/yosys/abc9_map.v
- share/yosys/abc9_model.v
- share/yosys/abc9_unmap.v
- share/yosys/achronix/speedster22i/cells_map.v
- share/yosys/achronix/speedster22i/cells_sim.v
- share/yosys/adff2dff.v
- share/yosys/anlogic/arith_map.v
- share/yosys/anlogic/brams.txt
- share/yosys/anlogic/brams_map.v
- share/yosys/anlogic/cells_map.v
- share/yosys/anlogic/cells_sim.v
- share/yosys/anlogic/eagle_bb.v
- share/yosys/anlogic/lutrams.txt
- share/yosys/anlogic/lutrams_map.v
- share/yosys/cells.lib
- share/yosys/choices/han-carlson.v
- share/yosys/choices/kogge-stone.v
- share/yosys/choices/sklansky.v
- share/yosys/cmp2lcu.v
- share/yosys/cmp2lut.v
- share/yosys/cmp2softlogic.v
- share/yosys/coolrunner2/cells_counter_map.v
- share/yosys/coolrunner2/cells_latch.v
- share/yosys/coolrunner2/cells_sim.v
- share/yosys/coolrunner2/tff_extract.v
- share/yosys/coolrunner2/xc2_dff.lib
- share/yosys/dff2ff.v
- share/yosys/ecp5/arith_map.v
- share/yosys/ecp5/brams.txt
- share/yosys/ecp5/brams_map.v
- share/yosys/ecp5/cells_bb.v
- share/yosys/ecp5/cells_ff.vh
- share/yosys/ecp5/cells_io.vh
- share/yosys/ecp5/cells_map.v
- share/yosys/ecp5/cells_sim.v
- share/yosys/ecp5/dsp_map.v
- share/yosys/ecp5/latches_map.v
- share/yosys/ecp5/lutrams.txt
- share/yosys/ecp5/lutrams_map.v
- share/yosys/efinix/arith_map.v
- share/yosys/efinix/brams.txt
- share/yosys/efinix/brams_map.v
- share/yosys/efinix/cells_map.v
- share/yosys/efinix/cells_sim.v
- share/yosys/efinix/gbuf_map.v
- share/yosys/fabulous/arith_map.v
- share/yosys/fabulous/cells_map.v
- share/yosys/fabulous/ff_map.v
- share/yosys/fabulous/io_map.v
- share/yosys/fabulous/latches_map.v
- share/yosys/fabulous/prims.v
- share/yosys/fabulous/ram_regfile.txt
- share/yosys/fabulous/regfile_map.v
- share/yosys/gate2lut.v
- share/yosys/gatemate/arith_map.v
- share/yosys/gatemate/brams.txt
- share/yosys/gatemate/brams_init_20.vh
- share/yosys/gatemate/brams_init_40.vh
- share/yosys/gatemate/brams_map.v
- share/yosys/gatemate/cells_bb.v
- share/yosys/gatemate/cells_sim.v
- share/yosys/gatemate/inv_map.v
- share/yosys/gatemate/lut_map.v
- share/yosys/gatemate/lut_tree_cells.genlib
- share/yosys/gatemate/lut_tree_map.v
- share/yosys/gatemate/mul_map.v
- share/yosys/gatemate/mux_map.v
- share/yosys/gatemate/reg_map.v
- share/yosys/gowin/arith_map.v
- share/yosys/gowin/brams.txt
- share/yosys/gowin/brams_map.v
- share/yosys/gowin/cells_map.v
- share/yosys/gowin/cells_sim.v
- share/yosys/gowin/cells_xtra_gw1n.v
- share/yosys/gowin/cells_xtra_gw2a.v
- share/yosys/gowin/cells_xtra_gw5a.v
- share/yosys/gowin/lutrams.txt
- share/yosys/gowin/lutrams_map.v
- share/yosys/greenpak4/cells_blackbox.v
- share/yosys/greenpak4/cells_latch.v
- share/yosys/greenpak4/cells_map.v
- share/yosys/greenpak4/cells_sim.v
- share/yosys/greenpak4/cells_sim_ams.v
- share/yosys/greenpak4/cells_sim_digital.v
- share/yosys/greenpak4/cells_sim_wip.v
- share/yosys/greenpak4/gp_dff.lib
- share/yosys/ice40/abc9_model.v
- share/yosys/ice40/arith_map.v
- share/yosys/ice40/brams.txt
- share/yosys/ice40/brams_map.v
- share/yosys/ice40/cells_map.v
- share/yosys/ice40/cells_sim.v
- share/yosys/ice40/dsp_map.v
- share/yosys/ice40/ff_map.v
- share/yosys/ice40/latches_map.v
The first 100 are listed.
distinfo 1
| File | Size | SHA256 |
|---|---|---|
| YosysHQ-yosys-v0.52_GH0.tar.gz | 3.295413e+06 | b6212f132edb4127099406ebdd1c6aee0f5db4175d8ce44053c45089e00dabbe |